Streamlining Design-to-Tester Pattern Conversion

Test engineers are almost always working against unrealistic schedules.  Think about it – we’re at the end of the product development process.  Delays in design, tape-out, and fab happen yet the schedule marches on.  And the schedule, which was likely based on a best-case scenario, is what the customer (or market timing) requires, so regardless of what happened up the line we still have to meet the same dates.  Something has to give and the result is almost always to push on the test engineering team to make up the time.

One of the biggest time sinks in the test development process is ATE pattern conversion.  The process of turning design simulations (VCDs, EVCDs) into operational, repeatable ATE test patterns can be complicated, time consuming, and frustrating.  I’m not talking about DFT tests (Scan) – these are usually straightforward because the input files are already cyclized (typically WGL or STIL), meaning the transition of signals and waveforms are synchronized to a defined system clock.  VCD files are event dump files where the transitions of pins and waveforms fire according to the simulation and the resulting state-changes show up as a pin name and time-stamp.  There is no notion of system time or cyclization in a VCD so the test engineer has to figure this out and convert the files into something that will load and run on an ATE.

What makes the process so hard?  Design simulations contain a lot of information and some of the information may be irrelevant (don’t care) to the test engineer.  Many times internal nodes are dumped along with external pins adding to the confusion and complexity of the output pattern.  Other times, internal nodes may be needed by the test engineer (IO transitions in VCDs for example) but are left out of the simulation dump.  Output pins or buses may contain simulation initialization information that is meaningless in the real operation of the device (activity during PLL lock).  Bidirectional pins may change state or direction in the simulation, resulting in very fast, transient events that clearly show up in the VCD waveforms but are a complete ‘don’t care’ from the designer’s perspective. And then there’s the time resolution of the simulation – when set to a very small value (femto-seconds) the times for events become very precise. Imagine a bus with 32 pins, each changing state or direction, each event logged to the femto-second.  The resulting bus transitions and state changes often appear to be smeared relative to time.

So what’s the solution?  There are a few software packages that advertise the ability to get a jump on this process and allow you to simulate the interaction of the tester and the design simulation.  While these can be effective and may help cut the debug time down, much of the efficacy may be attributed to the increased scrutiny and communication with verification and design earlier in the process.  However, the cost of these software packages and the increased bandwidth required by design and verification may make this option out of reach.

At Test Spectrum, we quickly figured out while doing contract test development (where you eat or starve based on your ability to provide realistic schedules) to not take this part of the process for granted.  After several iterations of pattern spins on several different projects, we put together guidelines for generating VCD files that are intended for use at test.  It provides recommendations on how to avoid many of the common problems test engineers encounter, whether converting patterns for simple, well understood bus types or highly custom, multi-time domain digital interfaces.

The guidelines start the dialog early in the project and get everyone thinking about how the entire process will work together.  We then try to start with a single, representative VCD simulation to test out the pattern conversion process.    When possible, we will reverse generate a VCD or test bench file from the converted input and ask verification to import and validate any conditioning steps that were done to create the pattern.  Many times simple environment settings and process changes made by verification can reduce the pattern processing and debug time substantially.

Early interaction with design and verification along with the simple act of opening the one of the VCD files, taking a good look at what is there, and setting up the conversion environment can be very effective for reducing the number of pattern spins and shorten the debug time.

To learn more, download the guidelines here:  “VCD Pattern Generation and Conversion Guidelines” 

In addition, if you need a tool to convert VCD simulations into ATE tester patterns, you should check out VectorPro and VectorPort.